ATLAS Off Detector Electronics
TTC Interface Module - TIM
John Lane, Martin Postranecky, Matthew Warren, Jon Butterworth, Dominic Hayes
The TIM (TTC Interface Module) is the interface between the SCT off-detector
electronics and the ATLAS Level-1 trigger. Each crate of ROD (Read-Out Driver)
modules contains a TIM, which receives the TTC (Timing, Trigger and Control)
signals, and transmits the required information to the RODs via a custom backplane.
The TIM is also capable of stand-alone operation, generating the signals as
requested by the local processor.
General Documentation
Beta User Documentation
- User Manual - Incomplete/Draft
- Test Software (for NIVXI)
- Physical Setup (txt):
TIM3A,
TIM2,
TIM1,
TIM0.
- Acceptance Testing/Sequence - Draft (txt):
TIM3A,
TIM2,
TIM1.
- PLD code currently seeing 'action'
v9 PLD code (all current users)
Directory (all) or Source:
1,
2,
3,
4a,
4b,
5,
6,
7,
8,
9.
Diagrams
Schematics and Layout
- TIM3A
Schematics (pdf)
Layout Tracks (pdf),
Power (pdf),
Silks (pdf),
Netlist (rpt),
Cadence Board (zip).
- TIM2 Schematics ALL (zip)
or Individual Sheets (.ps):
01-Backplane Connectors
02-PLD1 (VME), PLD2 (Stand-alone Mode)
03-PLD4a, PLD4b - Runmode ID Decoding
04-PLD5 (Serialiser, FIFO Control), PLD6 (J3 backplane map)
05-PLD7 (Sequencer), PLD8 (ROD busys)
06-PLD3 (Stand-Alone Mode Burst), PLD9 (TTCrx interface)
07-VME Interface
08-Clock Setup Delays and Serial Number
09-Trigger Window
10-LED FP drivers (RODBUSY)
11-Oscillators, Test Sw, TTXrx connector
12-FIFO, Sequencer RAM
13-Clock buffers and drivers
14-Busy Reciever, -5V converter
15-Ext NIM Inputs and Outputs
16-Ext ECL Inputs and Outputs
17-LED FP drivers (general)
- TIM2 Layout ALL (zip)
-Individual Layers (A3 ps):
01,
03,
04,
07,
08,
10,
VCC,
VEE+3V3,
GND-1,
GND-2.
-Assembly and Silkscreen (A3 ps):
Top-ASSY,
Top-SILK,
Bot-ASSY,
Bot-SILK,
Front-Panel.
-Netlist ( A4 TXT ).
-Cadence layout 4M zipped .brd file
(requires Allegro FREE Physical Viewer).
- TIM1 Schematics ALL (zip)
or Individual Sheets (.ps):
01,
02,
03,
04,
05,
06,
07,
08,
09,
10,
11,
12,
13,
14,
15,
16,
17
- TIM1 Layout ALL (zip)
Layer 01,
03,
04,
07,
08,
10,
VCC,
VEE+3V3,
GND-1,
GND-2,
TOP-ASSY,
TOP-SILK,
BOT-ASSY,
BOT-SILK,
Netlist,
.brd zipped.
More of John Lanes Docs and Diags
Preliminary documentation here
TIM context diagram (pdf)
TIM functional model (pdf)
Timing flow of SCT TTC signals (pdf)
Timing of TIM output signals (pdf)
Other Relevant pages
Updates
12 Jun 2004 - Fixed links
12 May 2004 - Updated 'pld code seeing action'
- Removed dead links from 'other relevant pages'
30 Jul 2003 - Added TIM3A Sch and PCB links
19 May 2003 - Fixed links after server move
24 Jan 2003 - Added TIMx link
.. Jan 2001 - I think this file was born the first draft on the web
Matthew Warren /
warren@hep.ucl.ac.uk