To further investigate the key open questions in High Energy Physics, it is planned to run the LHC at a much higher intensity from 2026 onwards, with the aim of increasing the amount of data collected by a factor of 100 compared to the first years of operation. This High Luminosity or HL-LHC poses a number of challenges. To increase the rate that data is collected at, it is necessary to upgrade the LHC to run at much higher intensities. This will result in approximately 200 collisions occuring simultaneously in the ATLAS detector every 25 nanoseconds, an order of magnitude more collisions than the ATLAS detector was designed for. To cope with this large increase in complexity, significant updates will be carried out to the ATLAS detector, especially the Inner Tracker dectector, which reconstructs the paths of charged particles as they travel through the detector. The UCL group plays a leading role in these upgrades, specifically in the following areas:
Hardware Track Trigger
Proton bunches collide in the ATLAS detector at a rate of about 40 million per second, but we can only write out around 1000 of these events. The selection of these events is carried out by the trigger. The fast and accurate performance of the trigger to select the small fraction of interesting events, whilst rejecting the large number of background events, is essential for the success of the ATLAS experiment. Making efficient use of the momentum and vertex information of the charged particle tracks reconstructed in the ATLAS Inner Tracking detector can provide the vital information necessary to obtain such performance. UCL pioneered the R&D for such a hardware-based track trigger at HL-LHC, has expertise across the board (pattern recognition, online tracking, tracker data acquisition and trigger) and continues to provide the co-leader of this ATLAS-wide project.
UCL has longstanding experience and is one of the leading groups in data acquisition (outputting the data from the hundred of millions of readout channels that make up the ATLAS detector). The latency and bandwidth requirements of the new upgraded Innter Tracking detector requires the use of custom application-specific integrated circuits (ASICs) and modern field-programmable gate arrays (FPGAs), UCL is a pioneer at exploiting such technologies to meet the exacting future data acquisition demands of the ATLAS detector.
Tracker design, simulation & performance studies
A tracker should be: cheap, massless, 100% hermetic & efficient, and have infinite granularity, bandwidth & lifetime ... When optimising the design of the upgraded Inner Tracking detector, it is necessary to balance these competiting requirements, for which a detailed simulation of the upgraded tracker is essential. To motivate the choices made, predictions of the physics reach are made for the different design options based on this simulation, which includes the conditions expected in the HL-LHC, along with optimised algorithms and analysis selections.
- Technical Design Report for the ATLAS ITk Strip Detector
- ATLAS Phase-II Upgrade Scoping Document
CERN-LHCC-2015-020 ; LHCC-G-166
- Letter of Intent for the Phase-II Upgrade of the ATLAS Experiment
CERN-LHCC-2012-022 ; LHCC-I-023
- European Committee for Future Accelerators (ECFA) Workshops
Key AcademicsProf. Nikos Konstantinidis
Dr Andreas Korn
Dr Tim Scanlon
Leadership PositionsProf. Nikos Konstantinidis Hardware Track Trigger - Coordinator 2008-present
Dr Andreas Korn ITK Simulation & Performance - Convener 2013-2016