The TIM (TTC Interface Module) is the interface between the SCT off-detector electronics and the ATLAS Level-1 trigger. Each crate of ROD (Read-Out Driver) modules contains a TIM, which receives the TTC (Timing, Trigger and Control) signals, and transmits the required information to the RODs via a custom backplane. The TIM is also capable of stand-alone operation, generating the signals as requested by the local processor.
TIM-3 is the final version of TIM. 24 TIM-3Cs (and lately more as TIM-3Fs) have been produced for all SCT and Pixel needs. A further batch have been manufactured by Muon groups (TIM-3E). TIM-3 differs from previous versions in that it uses FPGA programmable-logic (as opposed to CPLD on TIM-0/1/2). The firmware has been completely re-written in VHDL for this version.
Version 3C/E/F is the production TIM. This version is 99% back-wards compatible with TIM versions 1-3B, with software only requiring very minor modification for continued operation. TIM3 adds a large number of extra functions and increased flexibility, as well as compatibility with the TTCrq mezzanine. TIM1/2 specifics are detailed on their own page (see the sidebar).
TIM-3A is the pre-series version, and is no longer in use. TIM-3B was to be a low volume initial production run, but a pcb warp problem occurred. Although the reasons for this are thought to be understood and solvable by the manufacturer, the addition of extra stiffening bars seemed prudent and the TIM-3C was born. Functionally TIM-3B/C are identical, with the documentation here relevant to both, unless stated otherwise.
IMPORTANT - Firmware flashing: Versions of ISE >10 fail to program the PROMs on TIM-3Cs. There is a quick hack to fix this on ISE versions >10, please contact us, or read the last post here. Briefly: search for xc18v04.bsd in Xilinx installation directory. - change "Part Number" from 0101000000110110 to 0101000000100110 in the file (around line 152)
Mar 2012: Firmware version 0x26 added. Fixes FFTV vetoing TTC trigger. This includes new delay elements for TTC-L1A/BCR/ECR signals. Download here.
Aug 2011: Firmware version 0x20 added. Changed clocking to improve TTCrx TType integrity on TIM v3F. Available here.
Jul 2011: Firmware version 1F added (code dated 10/10/2008). This version is reduces L1A latency, but the pipeline remains. Available here.
Jan 2009: TIM 3F shipped to CERN.
Oct 2008: BUGFIX: No more double ECRs when using delay here.Sep 2008: Firmware Update! Version 1D. Added ECR pipeline. This is a drop-in replacement for 1B/1C. The new pipeline is enabled using the BCR pipeline enables. Available here.
July 2008: Even MORE new firmware! Version 1C. Fixed read-only TIM TType bits (9:8) in run-mode bug, set vRodBusy at reset, reduced latency of pipeline. See firmware section.
June 2008: More new firmware! Version 1B. Fixed internal trigger always random bug. Added BCR delay option. See firmware section.
May 2008: New firmware available. Version 1A. Fixed BCID-Offset rollover bug, increased BCID-Offset range and a little more. More info and downloads in the firmware section.
Latest Registers Description For older/specific versions see the firmware section.
User Manual (Incomplete/Draft)
Annotated photo showing basic functions. Older versions: TIM-3B, TIM-3A
TIM-3C (and E/F) Clock Flow [ TIM-3A version here]
Discrete's versus FPGA's
Version 26Fixes FFTV vetoing TTC trigger. This includes new delay elements for TTC-L1A/BCR/ECR signals. The new delay is more coherent: a setting of 0 = the minimum 1 clock delay. Thereafter the delays increase linearly. The option to add TTC signals to the stand-alone stream is now removed. Download FPGA2 version 0x26 here. Use the Register Description v26.
Version 20Changed TTC TType clocking for TIM v3F compatibility. Download FPGA2 version 0x20 here. Use the Register Description v1D.
Version 1FReduces pipeline disabled latency from 3 to 1 clock. Download FPGA2 version 1F here. Use the Register Description v1D.
Version 1EFixed double ECR when delaying TTC-ECRs. Download FPGA2 version 1E here. Use the Register Description v1D.
- Added ECR pipeline.The pipeline is enabled using the BCR pipeline enables (from version 1B) so this is a drop-in replacement for 1B/1C.
- Disabled deadtime veto when using stand-alone signals in run-mode.
Download the FPGA2 file here. Use the Register Description v1D.
- Fixed read-only TIM TType(9:8) in run-mode bug.
- Set vRodBusy at reset.
- Reduced the latency of the trigger and BCR pipelines.
- Fixed internal-trigger-always-randomised bug. BCR delay option added, including using TTC-BCR. FPGA2 Version 1B Firmware download here. Use the Register Description v1B.
- Notes on BCR Delay option:
In stand-alone mode BCR can be delayed by the same amount as the trigger. In run-mode
the TTC-BCR can be also delayed by diverting it to the stand-alone mode system (and delay).
See Enables3 Reg bits 13 and 14.
NB: Bit change: BCIDMaxEn now at bit 15. See Enables3 Reg.
- BCID handling improved. FPGA2 Version 1A Firmware download here. Use the Register Description v1A. This version is backwards-compatible with v19.
Bug fix: For (BCIDs < BCID-OFFSET) the BCID increments by 1. This has been corrected. (e.g. rollover was at 3564, now 3563).
BCID rollover at 4095 option added. See Enables3 Reg bit 13 (Note this bit moves in the next version, see above).
BCID offset range extended to the full 4095 range. This requires a new BCID-Offset Register. Note that writing to bits (3:0) of this register will still affect the old BCID offset bits in the BCID Reg and vice versa for complete compatibility with existing software.
I2C TTCrx clock rate reduced by a factor of 10 to 10MHz. This might reduce occurences of infective writes seen by SCT (although this problem was never seen in the lab). Users may see timeouts when waiting for an I2C access to complete.
Status-Latch glitch detection added. This affects Status-lch, Status3-lch and BusyStat3-lch. Momentary, sub clock period (1-25 ns) glitches now detected. Note that these register a 1 for any bit that changes, even briefly, since last cleared.
- Features for cosmics! FPGA2 Version 19 Firmware download here. Use the Register Description v19.
Bug fix: Using TTC-L1A in SA mode, with delay no longer causes BCID mismatches.
New func - TTC-TTypes can be used in SA mode, but only in conjunction with TTC-L1As. See Enables3 Reg bits 11,12.
- FPGA2 Version 16 Firmware download here.
- Bug fix of v14 - allows use of full 256 bit trigger pipeline.
FPGA2 Version 14 Firmware.
Use this firmware in conjunction with the TIM Register 14 Description.
This version impliments FFTV Local Emergency action. See bits in Busy Stat3 and Control registers.
Added a means to delay the TTC-L1A signal (although this can be complicated). See SaTtcL1aEn bit in Enables3 Reg.
Version 13This is the most tested version of TIM firmware and is considered stable. New features may be added to later versions, but this will not affect the functionality found here. In other words, software written for this version should not need to be changed as a result of a firmware upgrade.
FPGA2 Version 13 Firmware.
Our Xilinx Impact Configuration File.
FPGA2 Debug LED/pin assignments.
You may have wondered about the second FPGA on TIM - this is the VME controller and is seldom upgraded but included here for completeness:
FPGA1 Version 3 Firmware.
Use this firmware in conjunction with the TIM Register Description.
Reseting is now significantly longer (~700ms) - it assumes a clock switch, and starts a clock-switch-busy delay cycle to wait until all downstream PLLs have locked. After a reset wait until the ClkSwitchBusy bit in the (Busy Stat3 Reg) clears before proceeding.
The Burst Counter now has extra 16 bits allowing 32 bit bursts. (Burst Hi Reg).
L1ID can be set to rollover into ECR-ID (allows 32 bit Trigger counting). See L1IDroECRen bit (Enables3 Reg).
Burst bug-fixed so that it counts only outgoing triggers (e.g. post veto) This can be disabled with the PreBusyBurstEn bit (Enables3 Reg).
Trigger-Sequencer Mode allows all stand-alone trigger sources to be diverted to start the sequencer instead. This does not apply to TTC triggers and care should be taken when using the TRIO NIM output in this mode, as it will output the 'source' triggers. See the TrigSeqModeEn bit (Enables3 Reg). Usage Notes: Ensure that the sequencer triggers are enabled (Seq Ctl Reg). The sequencer is only re-startable after finishing it's cycle, so the Seq End Reg can be used to set a post trigs dead-time.
The Fixed-Frequency-Trigger-Veto can be further monitored using the (Vetoed-Trigger Counter Reg and the Veto Time Counter).
A second, much improved random number generator is now available. It is highly recommended you use this one over the original version. Set the frequency in the Control Reg, and enable it via the Random2En bit (Enables3 Reg). The internal triggers do NOT need to be enabled for Random2 operation.
- Firmware Source
The firmware for TIM-3 has been developed in VHDL using the Mentor Graphics FPGA Advantage (version 5.4) suite of tools. TIM3_Firmware_v20_src_2007-10-19.zip (10MB) contains an example of the source for the 4 libraries needed: TIM_lib, TIM_fftv, TIM_fpga1 and TIM_fpga2. Also required is the Xilinx "unisim" library. This code is for v20 (v19 with very minor mods). Please contact us if you would like the latest code (if it exists).
Older firmware can be browsed here if needed.
Physical Setup (txt) TIM-3C, TIM-3F, TIM-3C/E/F Photos (8M pdf), TIM-3B.
Acceptance Testing/Sequence (txt) TIM-3C/E/F, TIM-3B
Post-manufacture "Finishing-Off" Instruction (txt) TIM-3C/E/F.
- TIM 3C Schematics and Layout
Assembly: Top, Bottom, Silks, Drilling.
Kit List, Parts List, Order List, Netlist (.rpt)
Cadence physical (brd 8M)
- TIM-3E/F Schematics and Layout
All in PDF format unless stated.
Assembly: Top, Bottom, Drilling.
Kitting List, Parts List, Order List, Netlist (.rpt)
Cadence physical .brd (8M)
Schematics, Layout, Top Silk, Bottom Silk.
Parts List, Netlist (.rpt), Cadence physical (brd zip).
TIM 3A Setup, Schematics and Layout (zip)
Copyright © 2003-2022 UCL HEP ATLAS Electronics Group (last modified 19 Apr 2022)