TTC Interface Module for SCT & Pixel Detectors


The TIM (TTC Interface Module) is the interface between the SCT off-detector electronics and the ATLAS Level-1 trigger. Each crate of ROD (Read-Out Driver) modules contains a TIM, which receives the TTC (Timing, Trigger and Control) signals, and transmits the required information to the RODs via a custom backplane. The TIM is also capable of stand-alone operation, generating the signals as requested by the local processor.

TIM-3 is the final version of TIM. 24 TIM-3Cs (and lately more as TIM-3Fs) have been produced for all SCT and Pixel needs. A further batch have been manufactured by Muon groups (TIM-3E). TIM-3 differs from previous versions in that it uses FPGA programmable-logic (as opposed to CPLD on TIM-0/1/2). The firmware has been completely re-written in VHDL for this version.

Version 3C/E/F is the production TIM. This version is 99% back-wards compatible with TIM versions 1-3B, with software only requiring very minor modification for continued operation. TIM3 adds a large number of extra functions and increased flexibility, as well as compatibility with the TTCrq mezzanine. TIM1/2 specifics are detailed on their own page (see the sidebar).

TIM-3A is the pre-series version, and is no longer in use. TIM-3B was to be a low volume initial production run, but a pcb warp problem occurred. Although the reasons for this are thought to be understood and solvable by the manufacturer, the addition of extra stiffening bars seemed prudent and the TIM-3C was born. Functionally TIM-3B/C are identical, with the documentation here relevant to both, unless stated otherwise.


IMPORTANT - Firmware flashing: Versions of ISE >10 fail to program the PROMs on TIM-3Cs. There is a quick hack to fix this on ISE versions >10, please contact us, or read the last post here. Briefly: search for xc18v04.bsd in Xilinx installation directory. - change "Part Number" from 0101000000110110 to 0101000000100110 in the file (around line 152)

Mar 2012: Firmware version 0x26 added. Fixes FFTV vetoing TTC trigger. This includes new delay elements for TTC-L1A/BCR/ECR signals. Download here.

Aug 2011: Firmware version 0x20 added. Changed clocking to improve TTCrx TType integrity on TIM v3F. Available here.

Jul 2011: Firmware version 1F added (code dated 10/10/2008). This version is reduces L1A latency, but the pipeline remains. Available here.

Jan 2009: TIM 3F shipped to CERN.

Oct 2008: BUGFIX: No more double ECRs when using delay here.

Sep 2008: Firmware Update! Version 1D. Added ECR pipeline. This is a drop-in replacement for 1B/1C. The new pipeline is enabled using the BCR pipeline enables. Available here.

July 2008: Even MORE new firmware! Version 1C. Fixed read-only TIM TType bits (9:8) in run-mode bug, set vRodBusy at reset, reduced latency of pipeline. See firmware section.

June 2008: More new firmware! Version 1B. Fixed internal trigger always random bug. Added BCR delay option. See firmware section.

May 2008: New firmware available. Version 1A. Fixed BCID-Offset rollover bug, increased BCID-Offset range and a little more. More info and downloads in the firmware section.

All documents are PDF or HTML unless stated otherwise. Please contact us if you would prefer the 'source' (often Powerpoint or EPS).

  • TIM 3B Schematics and Layout
    Schematics, Layout, Top Silk, Bottom Silk.
    Parts List, Netlist (.rpt), Cadence physical (brd zip).

  • Archived TIM3 Docs
    TIM 3A Setup, Schematics and Layout (zip)