ATLAS TIM

Version 26

Version 20

Version 1F

Version 1E

Version 1D

• Added ECR pipeline.The pipeline is enabled using the BCR pipeline enables (from version 1B) so this is a drop-in replacement for 1B/1C.
• Disabled deadtime veto when using stand-alone signals in run-mode.

Download the FPGA2 file here. Use the Register Description v1D.

Version 1C

• Fixed read-only TIM TType(9:8) in run-mode bug.
• Set vRodBusy at reset.
• Reduced the latency of the trigger and BCR pipelines.

Version 1B

• Fixed internal-trigger-always-randomised bug. BCR delay option added, including using TTC-BCR. FPGA2 Version 1B Firmware download here. Use the Register Description v1B.
• Notes on BCR Delay option: In stand-alone mode BCR can be delayed by the same amount as the trigger. In run-mode the TTC-BCR can be also delayed by diverting it to the stand-alone mode system (and delay). See Enables3 Reg bits 13 and 14.
  NB: Bit change: BCIDMaxEn now at bit 15. See Enables3 Reg.
  
  

Version 1A

• BCID handling improved. FPGA2 Version 1A Firmware download here. Use the Register Description v1A. This version is backwards-compatible with v19.
• Notes:
  Bug fix: For (BCIDs < BCID-OFFSET) the BCID increments by 1. This has been corrected. (e.g. rollover was at 3564, now 3563).
  BCID rollover at 4095 option added. See Enables3 Reg bit 13 (Note this bit moves in the next version, see above).
  BCID offset range extended to the full 4095 range. This requires a new BCID-Offset Register. Note that writing to bits (3:0) of this register will still affect the old BCID offset bits in the BCID Reg and vice versa for complete compatibility with existing software.
  I2C TTCrx clock rate reduced by a factor of 10 to 10MHz. This might reduce occurences of infective writes seen by SCT (although this problem was never seen in the lab). Users may see timeouts when waiting for an I2C access to complete.
  Status-Latch glitch detection added. This affects Status-lch, Status3-lch and BusyStat3-lch. Momentary, sub clock period (1-25 ns) glitches now detected. Note that these register a 1 for any bit that changes, even briefly, since last cleared.
  

Version 19

• Features for cosmics! FPGA2 Version 19 Firmware download here. Use the Register Description v19.
• Notes:
  Bug fix: Using TTC-L1A in SA mode, with delay no longer causes BCID mismatches.
  New func - TTC-TTypes can be used in SA mode, but only in conjunction with TTC-L1As. See Enables3 Reg bits 11,12.
  

Version 16

• FPGA2 Version 16 Firmware download here.
• Bug fix of v14 - allows use of full 256 bit trigger pipeline.
  

Version 14

• Downloads:
  FPGA2 Version 14 Firmware.
  
  
• Notes:
  Use this firmware in conjunction with the TIM Register 14 Description.

  This version impliments FFTV Local Emergency action. See bits in Busy Stat3 and Control registers.

  Added a means to delay the TTC-L1A signal (although this can be complicated). See SaTtcL1aEn bit in Enables3 Reg.

Version 13

• Downloads:
  FPGA2 Version 13 Firmware.
  Our Xilinx Impact Configuration File.
  FPGA2 Debug LED/pin assignments.
  You may have wondered about the second FPGA on TIM - this is the VME controller and is seldom upgraded but included here for completeness:
  FPGA1 Version 3 Firmware.
• Notes:
  Use this firmware in conjunction with the TIM Register Description.

  Reseting is now significantly longer (~700ms) - it assumes a clock switch, and starts a clock-switch-busy delay cycle to wait until all downstream PLLs have locked. After a reset wait until the ClkSwitchBusy bit in the (Busy Stat3 Reg) clears before proceeding.

  The Burst Counter now has extra 16 bits allowing 32 bit bursts. (Burst Hi Reg).

  L1ID can be set to rollover into ECR-ID (allows 32 bit Trigger counting). See L1IDroECRen bit (Enables3 Reg).

  Burst bug-fixed so that it counts only outgoing triggers (e.g. post veto) This can be disabled with the PreBusyBurstEn bit (Enables3 Reg).

  Trigger-Sequencer Mode allows all stand-alone trigger sources to be diverted to start the sequencer instead. This does not apply to TTC triggers and care should be taken when using the TRIO NIM output in this mode, as it will output the 'source' triggers. See the TrigSeqModeEn bit (Enables3 Reg). Usage Notes: Ensure that the sequencer triggers are enabled (Seq Ctl Reg). The sequencer is only re-startable after finishing it's cycle, so the Seq End Reg can be used to set a post trigs dead-time.

  The Fixed-Frequency-Trigger-Veto can be further monitored using the (Vetoed-Trigger Counter Reg and the Veto Time Counter).

  A second, much improved random number generator is now available. It is highly recommended you use this one over the original version. Set the frequency in the Control Reg, and enable it via the Random2En bit (Enables3 Reg). The internal triggers do NOT need to be enabled for Random2 operation.

The firmware for TIM-3 has been developed in VHDL using the Mentor Graphics FPGA Advantage (version 5.4) suite of tools. TIM3_Firmware_v20_src_2007-10-19.zip (10MB) contains an example of the source for the 4 libraries needed: TIM_lib, TIM_fftv, TIM_fpga1 and TIM_fpga2. Also required is the Xilinx "unisim" library. This code is for v20 (v19 with very minor mods). Please contact us if you would like the latest code (if it exists).

Older firmware can be browsed here if needed.