ATLAS TIM

TIM-2/TIM-1

TIM-2 is a fully functional (as per specification) version of TIM. It is in wide use at SCT macro assembly sites, CERN SR1 and other test areas. This version was manufactured using now obsolete programmable-logic (Lattice Mach5 CPLDs), hence the more flexible TIM-3 design.

All documents are PDF unless stated otherwise. Please contact us if you would prefer the 'source' (often Powerpoint or EPS).

• Setup/Testing
  Physical Setup (txt): TIM-2, TIM-2B, TIM-2C, TIM-1.
  Acceptance Testing/Sequence: TIM-2, TIM-2B, TIM-2C, TIM-1.
  


• Firmware
  PLD code currently seeing 'action'
  
  • v9 (almost all users) Directory (all), Firmware (zip)
    Source: 1, 2, 3, 4a, 4b, 5, 6, 7, 8, 9.
    
  • v9_cern (CERN testbeam and assembly) Directory (all), Firmware (zip)
    Source: 1, 2, 3, 4a, 4b, 5, 6, 7, 8, 9.
    
    Older versions of TIM firmware can be found in the ./firmware directory.
  
  Firmware requires Lattice ispVM System software and cable to download.
  


• Diagrams
  Functions Picture
  Clocks Flow: TIM-2, TIM-1.
  Busy Flow
  TIM-2 Clock Sync Switch and Failover Logic
  PLDs versus ICs
  Fast Commands Flow
  Overall Flowcharts (4 pages)
  PLD Flowcharts (8 pages)
  VME Read and Write Logic Timing (NI-VXI) Read, Write
  


• TIM-2 Schematics
  ALL (zip)
  01-Backplane Connectors
  02-PLD1 (VME), PLD2 (Stand-alone Mode)
  03-PLD4a, PLD4b - Runmode ID Decoding
  04-PLD5 (Serialiser, FIFO Control), PLD6 (J3 backplane map)
  05-PLD7 (Sequencer), PLD8 (ROD busys)
  06-PLD3 (Stand-Alone Mode Burst), PLD9 (TTCrx interface)
  07-VME Interface
  08-Clock Setup Delays and Serial Number
  09-Trigger Window
  10-LED FP drivers (RODBUSY)
  11-Oscillators, Test Sw, TTXrx connector
  12-FIFO, Sequencer RAM
  13-Clock buffers and drivers
  14-Busy Reciever, -5V converter
  15-Ext NIM Inputs and Outputs
  16-Ext ECL Inputs and Outputs
  17-LED FP drivers (general)
  


• TIM-2 Layout
  ALL (zip) or Layer: 01, 03, 04, 07, 08, 10, Vcc, Vee+3V3, Gnd-1, Gnd-2, Top-Assy, Top-Silk, Bot-Assy, Bot-Silk, Front-Panel,
  Netlist
  
  Cadence physical layout (.brd zipped 4M) (requires Allegro FREE Physical Viewer).
  



• TIM-1 Schematics
  ALL (zip) or Page 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11, 12, 13, 14, 15, 16, 17
  


• TIM-1 Layout
  ALL (zip) or Layer 01, 03, 04, 07, 08, 10, Vcc, Vee+3V3, Gnd-1, Gnd-2, Top-Assy, Top-Silk, Bot-Assy, Bot-Silk,
  Netlist,
  
  Cadence physical layout (.brd zipped 4M) (requires Allegro FREE Physical Viewer)